A Dynamic Random Access Memory (DRAM) element generally includes a capacitor to store electric power and incorporates with a transistor switch to store varying charging data. It is fabricated in a matrix structure and collaborates with a bit line and word line to achieve dynamic random access function.
The capacitor usually is fabricated by etching a substrate to form a trench or forming individual conductive transistor and depositing to form conductive layers on or in individual cell in a stacking manner. With advance of manufacturing process, the fixture size is greatly shrunk and the size of single transistor is reduced, hence more transistors and capacitors can be accommodated on a given size of circuit board. As a result, manufacturing cost also is reduced. The capacitor in the memory has to maintain a constant charge capacity which is determined by the distance of two electrodes, area of the two electrodes and dielectric constant of the dielectric layer between the two electrodes. These factors make shrinking the size of capacitor more difficult, consequently shrinking the size of memory also is difficult. How to further reduce production cost depends on reducing manufacturing complexity and process.
U.S. publication Nos. 2004/0241954 entitled “Method for forming a crown capacitor” and 2011/0159662 entitled “Method for fabricating crown-shaped capacitor” respectively disclose a method to fabricate crown-shaped capacitors. They mainly adopt varying approaches to enlarge corresponding area of two opposing electrodes in a capacitor to increase the capacity of the capacitor. They have a drawback of requiring complicated manufacturing processes.
Moreover, aside from enlarging the corresponding area of the electrodes in a capacitor to increase the charge capacity, simplifying fabrication process also helps to increase production yield and reduce the cost. Please refer to FIGS. 1A through 1F for a conventional process of manufacturing a capacitor. First, on a support layer 1, an etching hole 2 is formed thereon to run through an oxide layer 3 connecting to the support layer 1 and a substrate 4 connecting to the oxide layer 3, and a hard photo mask formed by two photoresists is provided prior to the etching process; next, referring to FIG. 1B, a pillar layer 5 is formed on the surfaces of the etching hole 2 and support layer 1; then, referring to FIG. 1C, a protective layer 6 is formed on the surface of the support layer 1; thereafter, referring to FIG. 1D, a third photoresit 7 is formed to facilitate removal of the protective layer 6, pillar layer 5 and support layer 1 by etching as shown in FIG. 1E; and finally, referring to FIG. 1F, the oxide layer 3 is removed via a wet etching process to form a plurality of tubular pillars 8 to finish the upstream fabrication process of the capacitor; thereafter the following fabrication process of the capacitor can be proceeded.
The aforesaid method needs to provide three photoresists to form the upstream structure. Production cost is higher. Moreover, the tubular pillars 8 formed by the pillar layer 5 have a greater aspect ratio; during the final wet etching process of removing the oxide layer 3, viscous effect caused by pulling out the upstream structure from the etching solution results in bending of the tubular pillars 8. That could affect the manufacturing quality of the capacitor in downstream process and reduce the production yield.